This is another area where CXL offers an answer. Unless everything in a heterogenous computing system is running at maximum performance, memory resources can be left underutilized or “stranded.” With memory accounting for upward of half of server BOM costs, the ability to share memory resources in a flexible and scalable way will be key. Once memory bandwidth and capacity are delivered to individual CPUs, GPUs, and accelerators in a manner that provides for desired performance, efficient use of that memory must then be considered. Significant amounts of additional bandwidth and capacity can then be delivered to processors-above and beyond that of the main memory channels-to feed data to the rapidly increasing number of cores in multi-core processors.įigure 1 CXL provides memory bandwidth and capacity to processors to feed data to the rapidly increasing number of cores. In the 3.0 update, CXL offers multi-tiered (fabric-attached) switching to allow for highly scalable memory pooling and sharing.ĬXL’s pin-efficient architecture helps overcome the limitations of package scaling by providing more memory bandwidth and capacity. CXL 3.0 pushes data rates up to 64 GT/s using PAM4 signaling to leverage PCIe 6.0 for its physical interface. In 2022, the CXL Consortium released the CXL 3.0 specification, which includes new features capable of changing the way data centers are architected, boosting overall performance through enhanced scaling. With memory such a key enabler of steady computing growth, it is gratifying how the industry has coalesced around CXL as the technology to tackle these big data center memory challenges.ĬXL is a new interconnect standard that has been on an aggressive development roadmap to deliver increased performance and efficiency in data centers. This is a critical consideration for infrastructure-as-a-service (IaaS) applications and workloads that include AI/ML and in-memory databases.Įnter Compute Express Link (CXL). There are also practical limits imposed on memory capacity, given the finite number of DDR memory channels that you can add to the CPU.
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